This invention relates to data acquisition circuits, and, more particularly, to analog data acquisition circuits which are used to monitor the operational status of relatively simple electronic equipment.
Advances in solid state power electronics have allowed the increased use of sophisticated power conversion and switching devices in evermore complex and reliable power systems. As electronic power conversion and switching techniques improve and the numbers and functional capability of the associated devices increases, the need for a simple and reliable method of monitoring and controlling large numbers of these devices has developed. Moreover, these devices are often remotely located with respect to a central controller as well as other similar power system equipment. The method of linking the central controller to the remote power control devices is often a high speed data or communication bus with a specific protocol and format. One such data bus was established by military standard MIL-STD-1553B. The use of such a communication link provides a reliable method of transmitting control data to, and receiving status data from, various components throughout the system. A further advantage of the data bus approach is a reduction in weight and complexity of the interconnections within the power system. While the use of a high speed data bus has many advantages at the system level, one draw back is an increase in complexity of the equipment which must now interface with the data bus, usually as remote terminals.
A prior approach to the interface design involves the use of a standard interface circuit which contains the transceivers and protocol logic for the particular data bus. A microprocessor is generally the other major item required to decipher the incoming commands and provide the timing and control logic for transferring the data to the subsystem (controlled device) as well as for the retrieval and storage of data for transmission on the data bus. Usually a quick response requested by a high speed data bus requires a fast (high clock frequency) microprocessor with 16 bit wide data words to meet the interface requirements. This works well for a complex piece of equipment already containing a microprocessor where the only major addition to the unit is the specific interface circuit for the application. Many of the more advanced transceiver circuits are designed for microprocessor based applications with the required control and status signals for various processor types available. A problem arises when the equipment to be controlled is simple, such as a solid state relay with variable current limiting. The internal control logic for such a device is simple and is not based on a microprocessor. The addition of a processor for interface purposes would substantially increase the complexity and cost while lowering the reliability of the device. A further area of concern lies in the implementation of a microprocessor system. A circuit of interdependent, clocked devices could represent a problem in the electrically noisy environment inside a solid state power conversion or switching device.
An alternative to a full microprocessor based interface design must be flexible but not at the expense of simplicity. The interface design should not be more complex than the host device, but it must provide many of the desirable features of a more complex data bus interface design. These features include digital and analog data acquisition, digital and possibly analog data outputs, and enough flexibility to allow common application in many different types of simple power conversion and switching equipment. In addition, the design must be noise immune and small in size to be compatible with the application. Such high speed data bus interfaces require the capability for acquiring analog data on a continuous basis. It is desirable to sense, digitize and store multiple analog signals for metering and monitoring of electrically simple power system components such as remote power controllers, remote bus interfaces, and solid state power controllers. Due to a relatively large number of these types of components in a typical power system, each of which would be communicating directly with a common high speed data bus controller, there is a desire to minimize data transmission time and overhead in the controlling device. Typical data acquisition systems for these applications use one of two usual methods of data collection with power system components in a complex system. The first is a dedicated wire from the monitor point to the metering device. While this is the most simple, direct approach, it becomes unmanageable when multiplied by tens or hundreds of metering points. Such an approach would ultimately sacrifice overall system weight and simplicity. A second approach is used when the power system component is electrically complex, (i.e., contains a microprocessor) and the analog data is multiplexed into the equipment hardware via the normal data acquisition techniques typical of microprocessor based designs.
The above methods of analog data acquisition are not acceptable for use in power systems having simple components where the number of dedicated wires would be prohibitive and a microprocessor is not used in the basic equipment design. Such high speed data bus interfaces require a free standing analog data acquisition circuit capable of monitoring a preselected number of channels (for example, 16) of data at a speed compatible with the operating frequency of the power system which may range between DC and 20 kHz. The circuit must be self starting and astable in operation since no outside control logic is found in the monitored devices. The circuit must also be gated (i.e. turned on and off) by signals from a data bus transceiver. In addition, the circuit must provide accuracy adequate for the application, with a digital output for data bus interface compatibility. The data must be formatted in such a way as to minimize data bus traffic and reduce data bus controller overhead. The present invention seeks to provide a simple high speed data bus interface which contains the above attributes.